00001 #ifndef __NV40_SHADER_H__
00002 #define __NV40_SHADER_H__
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028
00029
00030
00031
00032
00033
00034
00035
00036 #define NV40_VP_INST_VEC_RESULT (1 << 30)
00037 #define NV40_VP_INST_COND_UPDATE_ENABLE ((1 << 14)|1<<29)
00038 #define NV40_VP_INST_INDEX_INPUT (1 << 27)
00039 #define NV40_VP_INST_COND_REG_SELECT_1 (1 << 25)
00040 #define NV40_VP_INST_ADDR_REG_SELECT_1 (1 << 24)
00041 #define NV40_VP_INST_SRC2_ABS (1 << 23)
00042 #define NV40_VP_INST_SRC1_ABS (1 << 22)
00043 #define NV40_VP_INST_SRC0_ABS (1 << 21)
00044 #define NV40_VP_INST_VEC_DEST_TEMP_SHIFT 15
00045 #define NV40_VP_INST_VEC_DEST_TEMP_MASK (0x1F << 15)
00046 #define NV40_VP_INST_COND_TEST_ENABLE (1 << 13)
00047 #define NV40_VP_INST_COND_SHIFT 10
00048 #define NV40_VP_INST_COND_MASK (0x7 << 10)
00049 # define NV40_VP_INST_COND_FL 0
00050 # define NV40_VP_INST_COND_LT 1
00051 # define NV40_VP_INST_COND_EQ 2
00052 # define NV40_VP_INST_COND_LE 3
00053 # define NV40_VP_INST_COND_GT 4
00054 # define NV40_VP_INST_COND_NE 5
00055 # define NV40_VP_INST_COND_GE 6
00056 # define NV40_VP_INST_COND_TR 7
00057 #define NV40_VP_INST_COND_SWZ_X_SHIFT 8
00058 #define NV40_VP_INST_COND_SWZ_X_MASK (3 << 8)
00059 #define NV40_VP_INST_COND_SWZ_Y_SHIFT 6
00060 #define NV40_VP_INST_COND_SWZ_Y_MASK (3 << 6)
00061 #define NV40_VP_INST_COND_SWZ_Z_SHIFT 4
00062 #define NV40_VP_INST_COND_SWZ_Z_MASK (3 << 4)
00063 #define NV40_VP_INST_COND_SWZ_W_SHIFT 2
00064 #define NV40_VP_INST_COND_SWZ_W_MASK (3 << 2)
00065 #define NV40_VP_INST_COND_SWZ_ALL_SHIFT 2
00066 #define NV40_VP_INST_COND_SWZ_ALL_MASK (0xFF << 2)
00067 #define NV40_VP_INST_ADDR_SWZ_SHIFT 0
00068 #define NV40_VP_INST_ADDR_SWZ_MASK (0x03 << 0)
00069 #define NV40_VP_INST0_KNOWN ( \
00070 NV40_VP_INST_INDEX_INPUT | \
00071 NV40_VP_INST_COND_REG_SELECT_1 | \
00072 NV40_VP_INST_ADDR_REG_SELECT_1 | \
00073 NV40_VP_INST_SRC2_ABS | \
00074 NV40_VP_INST_SRC1_ABS | \
00075 NV40_VP_INST_SRC0_ABS | \
00076 NV40_VP_INST_VEC_DEST_TEMP_MASK | \
00077 NV40_VP_INST_COND_TEST_ENABLE | \
00078 NV40_VP_INST_COND_MASK | \
00079 NV40_VP_INST_COND_SWZ_ALL_MASK | \
00080 NV40_VP_INST_ADDR_SWZ_MASK)
00081
00082
00083 #define NV40_VP_INST_VEC_OPCODE_SHIFT 22
00084 #define NV40_VP_INST_VEC_OPCODE_MASK (0x1F << 22)
00085 # define NV40_VP_INST_OP_NOP 0x00
00086 # define NV40_VP_INST_OP_MOV 0x01
00087 # define NV40_VP_INST_OP_MUL 0x02
00088 # define NV40_VP_INST_OP_ADD 0x03
00089 # define NV40_VP_INST_OP_MAD 0x04
00090 # define NV40_VP_INST_OP_DP3 0x05
00091 # define NV40_VP_INST_OP_DP4 0x07
00092 # define NV40_VP_INST_OP_DPH 0x06
00093 # define NV40_VP_INST_OP_DST 0x08
00094 # define NV40_VP_INST_OP_MIN 0x09
00095 # define NV40_VP_INST_OP_MAX 0x0A
00096 # define NV40_VP_INST_OP_SLT 0x0B
00097 # define NV40_VP_INST_OP_SGE 0x0C
00098 # define NV40_VP_INST_OP_ARL 0x0D
00099 # define NV40_VP_INST_OP_FRC 0x0E
00100 # define NV40_VP_INST_OP_FLR 0x0F
00101 # define NV40_VP_INST_OP_SEQ 0x10
00102 # define NV40_VP_INST_OP_SFL 0x11
00103 # define NV40_VP_INST_OP_SGT 0x12
00104 # define NV40_VP_INST_OP_SLE 0x13
00105 # define NV40_VP_INST_OP_SNE 0x14
00106 # define NV40_VP_INST_OP_STR 0x15
00107 # define NV40_VP_INST_OP_SSG 0x16
00108 # define NV40_VP_INST_OP_ARR 0x17
00109 # define NV40_VP_INST_OP_ARA 0x18
00110 # define NV40_VP_INST_OP_TXWHAT 0x19
00111 #define NV40_VP_INST_SCA_OPCODE_SHIFT 27
00112 #define NV40_VP_INST_SCA_OPCODE_MASK (0x1F << 27)
00113 # define NV40_VP_INST_OP_RCP 0x02
00114 # define NV40_VP_INST_OP_RCC 0x03
00115 # define NV40_VP_INST_OP_RSQ 0x04
00116 # define NV40_VP_INST_OP_EXP 0x05
00117 # define NV40_VP_INST_OP_LOG 0x06
00118 # define NV40_VP_INST_OP_LIT 0x07
00119 # define NV40_VP_INST_OP_BRA 0x09
00120 # define NV40_VP_INST_OP_CAL 0x0B
00121 # define NV40_VP_INST_OP_RET 0x0C
00122 # define NV40_VP_INST_OP_LG2 0x0D
00123 # define NV40_VP_INST_OP_EX2 0x0E
00124 # define NV40_VP_INST_OP_SIN 0x0F
00125 # define NV40_VP_INST_OP_COS 0x10
00126 # define NV40_VP_INST_OP_PUSHA 0x13
00127 # define NV40_VP_INST_OP_POPA 0x14
00128 #define NV40_VP_INST_CONST_SRC_SHIFT 12
00129 #define NV40_VP_INST_CONST_SRC_MASK (0xFF << 12)
00130 #define NV40_VP_INST_INPUT_SRC_SHIFT 8
00131 #define NV40_VP_INST_INPUT_SRC_MASK (0x0F << 8)
00132 # define NV40_VP_INST_IN_POS 0
00133 # define NV40_VP_INST_IN_WEIGHT 1
00134 # define NV40_VP_INST_IN_NORMAL 2
00135 # define NV40_VP_INST_IN_COL0 3
00136 # define NV40_VP_INST_IN_COL1 4
00137 # define NV40_VP_INST_IN_FOGC 5
00138 # define NV40_VP_INST_IN_TC0 8
00139 # define NV40_VP_INST_IN_TC(n) (8+n)
00140 #define NV40_VP_INST_SRC0H_SHIFT 0
00141 #define NV40_VP_INST_SRC0H_MASK (0xFF << 0)
00142 #define NV40_VP_INST1_KNOWN ( \
00143 NV40_VP_INST_VEC_OPCODE_MASK | \
00144 NV40_VP_INST_SCA_OPCODE_MASK | \
00145 NV40_VP_INST_CONST_SRC_MASK | \
00146 NV40_VP_INST_INPUT_SRC_MASK | \
00147 NV40_VP_INST_SRC0H_MASK \
00148 )
00149
00150
00151 #define NV40_VP_INST_SRC0L_SHIFT 23
00152 #define NV40_VP_INST_SRC0L_MASK (0x1FF << 23)
00153 #define NV40_VP_INST_SRC1_SHIFT 6
00154 #define NV40_VP_INST_SRC1_MASK (0x1FFFF << 6)
00155 #define NV40_VP_INST_SRC2H_SHIFT 0
00156 #define NV40_VP_INST_SRC2H_MASK (0x3F << 0)
00157 #define NV40_VP_INST_IADDRH_SHIFT 0
00158 #define NV40_VP_INST_IADDRH_MASK (0x1F << 0)
00159
00160
00161 #define NV40_VP_INST_IADDRL_SHIFT 29
00162 #define NV40_VP_INST_IADDRL_MASK (7 << 29)
00163 #define NV40_VP_INST_SRC2L_SHIFT 21
00164 #define NV40_VP_INST_SRC2L_MASK (0x7FF << 21)
00165 #define NV40_VP_INST_SCA_WRITEMASK_SHIFT 17
00166 #define NV40_VP_INST_SCA_WRITEMASK_MASK (0xF << 17)
00167 # define NV40_VP_INST_SCA_WRITEMASK_X (1 << 20)
00168 # define NV40_VP_INST_SCA_WRITEMASK_Y (1 << 19)
00169 # define NV40_VP_INST_SCA_WRITEMASK_Z (1 << 18)
00170 # define NV40_VP_INST_SCA_WRITEMASK_W (1 << 17)
00171 #define NV40_VP_INST_VEC_WRITEMASK_SHIFT 13
00172 #define NV40_VP_INST_VEC_WRITEMASK_MASK (0xF << 13)
00173 # define NV40_VP_INST_VEC_WRITEMASK_X (1 << 16)
00174 # define NV40_VP_INST_VEC_WRITEMASK_Y (1 << 15)
00175 # define NV40_VP_INST_VEC_WRITEMASK_Z (1 << 14)
00176 # define NV40_VP_INST_VEC_WRITEMASK_W (1 << 13)
00177 #define NV40_VP_INST_SCA_RESULT (1 << 12)
00178 #define NV40_VP_INST_SCA_DEST_TEMP_SHIFT 7
00179 #define NV40_VP_INST_SCA_DEST_TEMP_MASK (0x1F << 7)
00180 #define NV40_VP_INST_DEST_SHIFT 2
00181 #define NV40_VP_INST_DEST_MASK (31 << 2)
00182 # define NV40_VP_INST_DEST_POS 0
00183 # define NV40_VP_INST_DEST_COL0 1
00184 # define NV40_VP_INST_DEST_COL1 2
00185 # define NV40_VP_INST_DEST_BFC0 3
00186 # define NV40_VP_INST_DEST_BFC1 4
00187 # define NV40_VP_INST_DEST_FOGC 5
00188 # define NV40_VP_INST_DEST_PSZ 6
00189 # define NV40_VP_INST_DEST_TC0 7
00190 # define NV40_VP_INST_DEST_TC(n) (7+n)
00191 # define NV40_VP_INST_DEST_TEMP 0x1F
00192 #define NV40_VP_INST_INDEX_CONST (1 << 1)
00193 #define NV40_VP_INST_UNK_00 (1 << 0)
00194 #define NV40_VP_INST3_KNOWN ( \
00195 NV40_VP_INST_SRC2L_MASK |\
00196 NV40_VP_INST_SCA_WRITEMASK_MASK |\
00197 NV40_VP_INST_VEC_WRITEMASK_MASK |\
00198 NV40_VP_INST_SCA_DEST_TEMP_MASK |\
00199 NV40_VP_INST_DEST_MASK |\
00200 NV40_VP_INST_INDEX_CONST)
00201
00202
00203 #define NV40_VP_SRC0_HIGH_SHIFT 9
00204 #define NV40_VP_SRC0_HIGH_MASK 0x0001FE00
00205 #define NV40_VP_SRC0_LOW_MASK 0x000001FF
00206 #define NV40_VP_SRC2_HIGH_SHIFT 11
00207 #define NV40_VP_SRC2_HIGH_MASK 0x0001F800
00208 #define NV40_VP_SRC2_LOW_MASK 0x000007FF
00209
00210
00211 #define NV40_VP_SRC_NEGATE (1 << 16)
00212 #define NV40_VP_SRC_SWZ_X_SHIFT 14
00213 #define NV40_VP_SRC_SWZ_X_MASK (3 << 14)
00214 #define NV40_VP_SRC_SWZ_Y_SHIFT 12
00215 #define NV40_VP_SRC_SWZ_Y_MASK (3 << 12)
00216 #define NV40_VP_SRC_SWZ_Z_SHIFT 10
00217 #define NV40_VP_SRC_SWZ_Z_MASK (3 << 10)
00218 #define NV40_VP_SRC_SWZ_W_SHIFT 8
00219 #define NV40_VP_SRC_SWZ_W_MASK (3 << 8)
00220 #define NV40_VP_SRC_SWZ_ALL_SHIFT 8
00221 #define NV40_VP_SRC_SWZ_ALL_MASK (0xFF << 8)
00222 #define NV40_VP_SRC_TEMP_SRC_SHIFT 2
00223 #define NV40_VP_SRC_TEMP_SRC_MASK (0x1F << 2)
00224 #define NV40_VP_SRC_REG_TYPE_SHIFT 0
00225 #define NV40_VP_SRC_REG_TYPE_MASK (3 << 0)
00226 # define NV40_VP_SRC_REG_TYPE_UNK0 0
00227 # define NV40_VP_SRC_REG_TYPE_TEMP 1
00228 # define NV40_VP_SRC_REG_TYPE_INPUT 2
00229 # define NV40_VP_SRC_REG_TYPE_CONST 3
00230
00231 #endif