fragment program opcode

Each fragment program opcode appears to be comprised of 4 32-bit values.

0 - Opcode, output reg/mask, ATTRIB source
1 - Source 0
2 - Source 1
3 - Source 2

There appears to be no special difference between result regs and temp regs. result.color == R0.xyzw result.depth == R1.z When the fragprog contains instructions to write depth, NV30_TCL_PRIMITIVE_3D_UNK1D78=0 otherwise it is set to 1.

Constants are inserted directly after the instruction that uses them.

It appears that it's not possible to use two input registers in one instruction as the input sourcing is done in the instruction dword and not the source selection dwords. As such instructions such as:

ADD result.color, fragment.color, fragment.texcoord[0];

must be split into two MOV's and then an ADD (nvidia does this) but I'm not sure why it's not just one MOV and then source the second input in the ADD instruction..

Negation of the full source is done with NV40_FP_REG_NEGATE, arbitrary negation requires multiplication with a const.

Arbitrary swizzling is supported with the exception of SWIZZLE_ZERO/SWIZZLE_ONE The temp/result regs appear to be initialised to (0.0, 0.0, 0.0, 0.0) as SWIZZLE_ZERO is implemented simply by not writing to the relevant components of the destination.

Looping

Loops appear to be fairly expensive on NV40 at least, the proprietary driver goes to a lot of effort to avoid using the native looping instructions. If the total number of *executed* instructions between REP/ENDREP or LOOP/ENDLOOP is <=500, the driver will unroll the loop. The maximum loop count is 255.

Todo:

Conditional execution

Non-native instructions: LIT LRP - MAD+MAD SUB - ADD, negate second source RSQ - LG2 + EX2 POW - LG2 + MUL + EX2 SCS - COS + SIN XPD DP2 - MUL + ADD NRM

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